343 lines
13 KiB
Python
343 lines
13 KiB
Python
import logging
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from ScEpTIC import tools
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from ScEpTIC.AST.elements.instruction import Instruction
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from ScEpTIC.exceptions import RuntimeException
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class BinaryOperation(Instruction):
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"""
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AST nodes for the LLVM Binary Instructions group
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https://llvm.org/docs/LangRef.html#binaryops
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NB: each result is stored as SIGNED int, even if the operation is unsigned.
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The sign bit is an interpretation of UNSIGNED operations, which will manage that by converting the int to its unsigned equivalent.
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"""
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def __init__(self, operation_type, first_operand, second_operand, target, is_bitwise, specific_attributes):
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super().__init__()
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self.operation_type = operation_type
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self.first_operand = first_operand
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self.second_operand = second_operand
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self.target = target
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self.is_bitwise = is_bitwise
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# just used to determine if a result is a "poison value", which is for back-end optimizations.
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self.exact = 'exact' in specific_attributes
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self.no_unsigned_wrap = 'nuw' in specific_attributes
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self.no_signed_wrap = 'nsw' in specific_attributes
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def __str__(self):
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retstr = super().__str__()
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retstr += '{} {}, {}'.format(self.operation_type, self.first_operand, self.second_operand)
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return retstr
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def get_input_lookup(self):
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"""
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Returns the input lookup data for the current operation
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"""
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first = self.first_operand.get_input_lookup()
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second = self.second_operand.get_input_lookup()
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return tools.merge_input_lookup_data(first, second)
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def get_val(self):
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"""
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Returns the value obtained from the operation.
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It converts address operands (if present) to relative spaces, applies the operation and converts them back to the absolute space.
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"""
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first_operand = self.first_operand.get_val()
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second_operand = self.second_operand.get_val()
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# address prefixes (populated if an operand is an address)
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prefix1 = None
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prefix2 = None
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# if first_operand is an address, get prefix and relative address (which can be used in operations)
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if self._vmstate.memory._is_absolute_address(first_operand):
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prefix1, first_operand = self._vmstate.memory._parse_absolute_address(first_operand)
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# if second_operand is an address, get prefix and relative address (which can be used in operations)
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if self._vmstate.memory._is_absolute_address(second_operand):
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prefix2, second_operand = self._vmstate.memory._parse_absolute_address(second_operand)
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# normalize prefixes: if one is none, just copy from the other.
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if prefix1 is None:
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prefix1 = prefix2
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elif prefix2 is None:
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prefix2 = prefix1
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val = self._get_val(first_operand, second_operand)
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# if prefix is set the result is an address, so I must convert it from relative to absolute space.
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if prefix1 is not None:
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# NB: prefixes must be the same
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if prefix1 != prefix2:
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raise RuntimeException('Uncompatible address space {} {} for binary operation {}.'.format(prefix1, prefix2, self.operation_type))
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val = self._vmstate.memory._convert_to_absolute_address(prefix1, val)
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logging.info('[{}] Executing {} {}, {} with result {}'.format(self.instruction_type, self.operation_type, first_operand, second_operand, val))
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return val
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def get_uses(self):
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"""
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Returns a list containing the names of the registers used by this instruction.
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(used by register allocation)
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"""
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first_reg = self.first_operand.get_uses()
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second_reg = self.second_operand.get_uses()
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return first_reg + second_reg
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def replace_reg_name(self, old_reg_name, new_reg_name):
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"""
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Replaces the name of a register used by the instruction with a new one.
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(used by register allocation)
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"""
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self.first_operand.replace_reg_name(old_reg_name, new_reg_name)
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self.second_operand.replace_reg_name(old_reg_name, new_reg_name)
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self.target.replace_reg_name(old_reg_name, new_reg_name)
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def _get_val(self, first_operand, second_operand):
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"""
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Returns the value returned from the operation, given its operands.
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"""
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dim = len(self.first_operand.type)
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if self.operation_type == 'add':
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# force encoding
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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val = first_operand + second_operand
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# force a number of bits
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return self.first_operand.convert_sint_to_sint(val, dim)
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elif self.operation_type == 'fadd':
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first_operand = float(first_operand)
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second_operand = float(second_operand)
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return first_operand + second_operand
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elif self.operation_type == 'sub':
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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val = first_operand - second_operand
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return self.first_operand.convert_sint_to_sint(val, dim)
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elif self.operation_type == 'fsub':
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first_operand = float(first_operand)
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second_operand = float(second_operand)
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return first_operand - second_operand
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elif self.operation_type == 'mul':
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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val = int(first_operand * second_operand)
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return self.first_operand.convert_sint_to_sint(val, dim)
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elif self.operation_type == 'fmul':
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first_operand = float(first_operand)
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second_operand = float(second_operand)
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return float(first_operand * second_operand)
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elif self.operation_type == 'udiv':
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# unsigned operations considers their operands as unsigned.
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# http://lists.llvm.org/pipermail/llvm-dev/2017-July/115975.html
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dim = len(self.first_operand)
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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first_operand = self.first_operand.convert_sint_to_uint(first_operand, dim)
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second_operand = self.second_operand.convert_sint_to_uint(second_operand, dim)
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val = int(first_operand // second_operand)
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# result is unsigned. Memory cells in my representation uses signed only.
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return self.first_operand.convert_uint_to_sint(val, dim)
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elif self.operation_type == 'sdiv':
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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val = int(first_operand // second_operand)
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return self.first_operand.convert_sint_to_sint(val, dim)
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elif self.operation_type == 'fdiv':
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return float(first_operand / second_operand)
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elif self.operation_type == 'urem':
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# unsigned operations considers their operands as unsigned.
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# http://lists.llvm.org/pipermail/llvm-dev/2017-July/115975.html
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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dim = len(self.first_operand)
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first_operand = self.first_operand.convert_sint_to_uint(first_operand, dim)
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second_operand = self.second_operand.convert_sint_to_uint(second_operand, dim)
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val = int(first_operand % second_operand)
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# result is unsigned. Memory cells in my representation uses signed only.
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return self.first_operand.convert_uint_to_sint(val, dim)
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elif self.operation_type == 'srem':
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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val = int(first_operand % second_operand)
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return self.first_operand.convert_sint_to_sint(val, dim)
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elif self.operation_type == 'frem':
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first_operand = float(first_operand)
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second_operand = float(second_operand)
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return float(first_operand % second_operand)
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elif self.operation_type == 'shl':
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# logic implemented to overcome discrepancies between signed and unsigned results
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# e.g. -1 << 2 != 65535 << 2 for 16bit operations
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first_operand = self.first_operand.convert_sint_to_bin(first_operand, dim)
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sh_len = int(second_operand)
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shifted = first_operand[sh_len:]+sh_len*'0'
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return self.first_operand.convert_bin_to_sint(shifted)
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elif self.operation_type == 'lshr':
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# logical shift right: append 0 to added left bits
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first_operand = self.first_operand.convert_sint_to_bin(first_operand, dim)
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sh_len = int(second_operand)
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shifted = sh_len*'0'+first_operand[:dim-sh_len]
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return self.first_operand.convert_bin_to_sint(shifted)
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elif self.operation_type == 'ashr':
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# arithmetical shift right: append sign bit to added left bits
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first_operand = self.first_operand.convert_sint_to_bin(first_operand, dim)
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sh_len = int(second_operand)
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shifted = sh_len*first_operand[0]+first_operand[:dim-sh_len]
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return self.first_operand.convert_bin_to_sint(shifted)
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elif self.operation_type == 'and':
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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return int(first_operand & second_operand)
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elif self.operation_type == 'or':
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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return int(first_operand | second_operand)
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elif self.operation_type == 'xor':
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first_operand = int(first_operand)
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second_operand = int(second_operand)
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return int(first_operand ^ second_operand)
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# if gets there, the operation is not supported right now.
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raise NotImplementedError('{} is not supported for now!'.format(self.operation_type))
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def resolve_memory_tag(self, elements):
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"""
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Resolves and returns the memory tag of the targeted element
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"""
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if self.memory_tag is None:
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if self.operation_type == 'add' or self.operation_type == 'fadd':
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operation_tag = '+'
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elif self.operation_type == 'sub' or self.operation_type == 'fsub':
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operation_tag = '-'
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elif self.operation_type == 'mul' or self.operation_type == 'fmul':
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operation_tag = '*'
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elif self.operation_type == 'udiv' or self.operation_type == 'sdiv' or self.operation_type == 'fdiv':
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operation_tag = '/'
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elif self.operation_type == 'urem' or self.operation_type == 'srem' or self.operation_type == 'frem':
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operation_tag = '%'
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elif self.operation_type == 'shl':
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operation_tag = '<<'
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elif self.operation_type == 'lshr' or self.operation_type == 'ashr':
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operation_tag = '>>'
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elif self.operation_type == 'and':
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operation_tag = '&&'
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elif self.operation_type == 'or':
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operation_tag = '||'
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elif self.operation_type == 'xor':
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operation_tag = '^'
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else:
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raise NotImplementedError(f"resolve_memory_tag() not implemented for binary operation type {self.operation_type}")
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first_operand_tag = self.first_operand.resolve_memory_tag(elements)
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second_operand_tag = self.second_operand.resolve_memory_tag(elements)
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self.memory_tag = f"{first_operand_tag} {operation_tag} {second_operand_tag}"
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return self.memory_tag
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def resolve_memory_tag_dependency(self, elements):
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if self.memory_tag_dependency is None:
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first_operand_tag = self.first_operand.resolve_memory_tag_dependency(elements)
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second_operand_tag = self.second_operand.resolve_memory_tag_dependency(elements)
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self.memory_tag_dependency = [first_operand_tag, second_operand_tag]
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return self.memory_tag_dependency
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def resolve_memory_address_chain(self, elements):
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"""
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Returns a list of all the instructions required to get the address of the targeted element(s)
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"""
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chain = []
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if self.target is not None:
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chain.append(self)
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chain.append(self.first_operand.resolve_memory_address_chain(elements))
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chain.append(self.second_operand.resolve_memory_address_chain(elements))
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return chain
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